Deskew fifo buffer with simplified initialization

Abstract

A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization. Moreover, the source-synchronization interface circuit includes control logic that initializes the source-synchronization interface circuit by operating the stages in the asynchronous FIFO buffer in a slow mode having a cycle time less than a data-transfer period for a predetermined number of clock cycles, and subsequently operating the stages in a normal mode having a cycle time that is less than that for the slow mode.