The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Apr. 21, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Lei Zhou, San Jose, CA (US);

Hiva Hedayati, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/00 (2006.01); H03K 5/15 (2006.01); H03K 19/00 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03K 5/15026 (2013.01); H03K 19/0013 (2013.01); H03M 1/121 (2013.01); H03M 1/46 (2013.01);
Abstract

A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.


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