The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Jun. 25, 2015
Applicant:

Rohm Co., Ltd., Ukyo-Ku, Kyoto, JP;

Inventor:

Masanobu Tsuji, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01); H03K 19/0185 (2006.01); H03K 19/00 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 19/0005 (2013.01); H03K 19/017509 (2013.01);
Abstract

An interface circuit receives an input signal IN having a first voltage amplitude from a first circuit, and outputs an output signal OUT having a second voltage amplitude to a second circuit. A level shifter comprises a first CMOS inverter and a second CMOS inverter which are cross-coupled, and a current limiting circuit that limits a current that flows through the first CMOS inverter and the second CMOS inverter, and converts the input signal IN into an intermediate signal INT which is a differential signal. A latch circuit receives the intermediate signal INT from the level shifter, and switches its state according to the positive signal and the negative signal of the intermediate signal INT.


Find Patent Forward Citations

Tsuji, Masanobu. (2017). Interface circuit (U.S. Patent No. 9584125). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9584125

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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