The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
May. 06, 2013
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Rajamani Sethuram, San Diego, CA (US);
Karim Arabi, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H03K 19/00 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0008 (2013.01); G01R 31/318342 (2013.01); G01R 31/318575 (2013.01); G06F 17/50 (2013.01); H03K 19/173 (2013.01);
Abstract
Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.