logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9583676 B1

PDFFull Text
Date of Patent:
Feb. 28, 2017

Filed:

Oct. 05, 2012

Low warpage wafer bonding through use of slotted substrates

Applicant:

Koninklijke Philips N.v., Eindhoven, NL;

Inventors:

Marc Andre De Samber, Someren, NL;

Eric Cornelis Egbertus Van Grunsven, Horst, NL;

Roy Antoin Bastiaan Engelen, Linburg, NL;

Assignee:

Koninklijke Philips N.V., Eindhoven, NL;

Attorney:
Primary Examiner:

Kimberly Rizkallah

Assistant Examiner:

Brian Turner

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 29/02 (2006.01); H01L 29/267 (2006.01); H01L 33/12 (2010.01); H01L 33/32 (2010.01); H01L 21/20 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 33/12 (2013.01); H01L 21/2007 (2013.01); H01L 33/0079 (2013.01);
Abstract

In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.

Find Patent Forward Citations

Loading…