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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9583573 B1

PDFFull Text
Date of Patent:
Feb. 28, 2017

Filed:

Oct. 31, 2014

Compound semiconductor device and method of fabricating the same

Applicant:

Formosa Epitaxy Incorporation, Taoyuan County, TW;

Inventors:

Chun-Ju Tun, Taoyuan County, TW;

Yi-Chao Lin, Taoyuan County, TW;

Chen-Fu Chiang, Taoyuan County, TW;

Cheng-Huang Kuo, Tainan, TW;

Assignee:

EPISTAR CORPORATION, Hsinchu, TW;

Attorney:

Patterson + Sheridan, LLP

Primary Examiner:

Jaehwan Oh

Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/36 (2006.01); H01L 21/266 (2006.01); H01L 21/02 (2006.01); H01L 31/0352 (2006.01); H01L 31/18 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/207 (2006.01); H01L 33/24 (2010.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/02439 (2013.01); H01L 21/02458 (2013.01); H01L 21/02639 (2013.01); H01L 21/2258 (2013.01); H01L 21/266 (2013.01); H01L 21/26546 (2013.01); H01L 29/201 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01); H01L 29/36 (2013.01); H01L 31/0352 (2013.01); H01L 31/1852 (2013.01); H01L 31/1856 (2013.01); H01L 33/24 (2013.01); Y02E 10/544 (2013.01); Y02P 70/521 (2015.11);
Abstract

A compound semiconductor device is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region; a semiconductor layer disposed on the substrate; and a buffer layer located between said substrate and said semiconductor layer; wherein doping conditions of said first doped region and said second doped region are different from each other; wherein said semiconductor layer has different thicknesses on locations corresponding to said first doped region and said second doped region respectively, and is formed as a structure with difference in thickness.

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