The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Oct. 02, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Hiroshi Nishikizawa, Tokyo, JP;
Takuro Homma, Tokyo, JP;
Hiraku Chakihara, Tokyo, JP;
Mitsuhiro Noguchi, Tokyo, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8246 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/45 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 21/265 (2006.01); H01L 21/283 (2006.01); H01L 21/311 (2006.01); H01L 21/32 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/265 (2013.01); H01L 21/283 (2013.01); H01L 21/28008 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/311 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32 (2013.01); H01L 21/3205 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/51 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.