The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Jan. 16, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventor:

Jeong-Mo Hwang, Colorado Springs, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01);
Abstract

A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a shared diffusion region formed in the surface of substrate between the channel of the MOS transistor and the channel of the memory transistor. A plasma oxide overlying the nitride layer and the surface of the substrate to form a top oxide layer over the nitride layer and a gate oxide layer over the surface of substrate in the second region.


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