The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Nov. 11, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Arifur Rahman, San Jose, CA (US);

Karthik Chandrasekar, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 27/06 (2006.01); G06F 17/50 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); H01L 23/528 (2013.01); H01L 27/0688 (2013.01); G06F 2217/06 (2013.01); G06F 2217/08 (2013.01); G06F 2217/40 (2013.01); G06F 2217/78 (2013.01);
Abstract

A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.


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