The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Nov. 25, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Srinivas Gandikota, Santa Clara, CA (US);

Zhendong Liu, San Jose, CA (US);

Jianxin Lei, Fremont, CA (US);

Rajkumar Jakkaraju, Sunnyvale, CA (US);

Assignee:

APPLIED MATERIALS, INC., Houston, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 21/285 (2013.01); H01L 21/28061 (2013.01); H01L 21/28568 (2013.01); H01L 21/76889 (2013.01); H01L 29/4941 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01); H01L 21/2855 (2013.01); H01L 27/10873 (2013.01);
Abstract

Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.


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