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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9583346 B1

PDFFull Text
Date of Patent:
Feb. 28, 2017

Filed:

Sep. 24, 2014

Method for manufacturing silicon carbide semiconductor device

Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Shunsuke Yamada, Osaka, JP;

Takeyoshi Masuda, Osaka, JP;

Taku Horii, Osaka, JP;

Assignee:

SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;

Attorney:

IPUSA, PLLC

Primary Examiner:

Scott B Geyer

Assistant Examiner:

SM. S Imtiaz

Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 21/324 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 29/872 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0475 (2013.01); H01L 21/046 (2013.01); H01L 21/324 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 29/872 (2013.01);
Abstract

A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.

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