The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 31, 2014
Applicant:

Egalax_empia Technology Inc., Taipei, TW;

Inventors:

Chin-Fu Chang, Taipei, TW;

Guang-Huei Lin, Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 27/02 (2006.01); H03K 5/00 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
G11C 27/026 (2013.01);
Abstract

A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities.


Find Patent Forward Citations

Chang, Chin-Fu. (2017). Positive/negative sampling and holding circuit (U.S. Patent No. 9583213). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9583213

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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