The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Sep. 26, 2014
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Omer Fainzilber, Even Yehuda, IL;

Eran Sharon, Rishon Lezion, IL;

Idan Alrod, Herzliya, IL;

Ariel Navon, Revava, IL;

Tz-Yi Liu, Palo Alto, CA (US);

Tianhong Yan, Saratoga, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 13/00 (2006.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); G11C 16/26 (2006.01); G11C 29/04 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G06F 11/1048 (2013.01); G11C 11/5642 (2013.01); G11C 16/3418 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); G11C 16/26 (2013.01); G11C 2013/005 (2013.01); G11C 2013/0057 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/5006 (2013.01); G11C 2213/71 (2013.01);
Abstract

A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.


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