The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Jul. 02, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jing Xie, San Diego, CA (US);

Yang Du, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/412 (2006.01); G11C 5/02 (2006.01); H01L 27/06 (2006.01); H01L 27/11 (2006.01); G11C 11/419 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 5/025 (2013.01); G11C 11/419 (2013.01); H01L 21/768 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 27/0688 (2013.01); H01L 27/11 (2013.01); H01L 27/1104 (2013.01); H01L 27/1108 (2013.01); H01L 27/1116 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.


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