The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 02, 2015
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Praveen Rajan Singh, Alphareatta, GA (US);

Yanbo Wang, Duluth, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01);
Abstract

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and (b) a combined resistive and capacitive load between the first and second differential write lines. The second circuit may be configured to (a) convert the first and the second differential write signals to a single-ended write signal and (b) present the single-ended write signal to the data bus.


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