The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 14, 2012
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventor:

Yoshimitsu Yamauchi, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01); G09G 3/32 (2016.01); G06F 1/32 (2006.01); G09G 3/20 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G06F 1/3265 (2013.01); G09G 3/2003 (2013.01); G09G 3/3233 (2013.01); G09G 3/3688 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); G09G 2300/0833 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0866 (2013.01); G09G 2300/0876 (2013.01); G09G 2310/0216 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0272 (2013.01); G09G 2320/0271 (2013.01); G09G 2320/066 (2013.01); G09G 2330/023 (2013.01);
Abstract

Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit () includes a first switch circuit () provided between a pixel node Np of a display element unit () and a data signal line SL, and a memory circuit () which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm. The memory circuit () includes a transistor Thaving a gate electrode connected to the storage node Nm, and a source electrode connected to the pixel node Np; a second switch circuit () which controls a conducting state between a drain electrode of the transistor Tand a voltage supply line VSL, in response to a signal level of a first control signal line SWL; a third switch circuit () which controls a conducting state between the drain electrode and the gate electrode of the transistor T, in response to a signal level of a second control signal line CSL; and a capacitor element Cst provided between the storage node Nm and the voltage supply line VSL.


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