The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Aug. 13, 2012
Applicants:

Bruce M. Fleischer, Bedford Hills, NY (US);

Thomas W. Fox, Hopewell Junction, NY (US);

Hans M. Jacobson, White Plains, NY (US);

Ravi Nair, Briarcliff Manor, NY (US);

Inventors:

Bruce M. Fleischer, Bedford Hills, NY (US);

Thomas W. Fox, Hopewell Junction, NY (US);

Hans M. Jacobson, White Plains, NY (US);

Ravi Nair, Briarcliff Manor, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 9/30 (2006.01); G06F 9/34 (2006.01);
U.S. Cl.
CPC ...
G06F 15/8076 (2013.01); G06F 9/30098 (2013.01); G06F 9/30109 (2013.01); G06F 9/34 (2013.01);
Abstract

An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.


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