The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Oct. 25, 2013
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Ganesh Suryanarayan Dasika, Austin, TX (US);

Rune Holm, Cambridge, GB;

Stephen John Hill, Cambridge, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 9/00 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A data processing devicecomprises a plurality of storage circuits, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumerwith a number of lanes. The consumer is able to individually access each of the plurality of storage circuitsin order to receive into the laneseither a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumeris also able to execute a common instruction of each of the plurality of lanes. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuitsstores at most y bits of each of the data elements. Furthermore, each of the storage circuitsstores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuitscomprise no more than b/y storage circuits.


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