The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Oct. 27, 2015
Applicant:

Silab Tech Pvt. Ltd., Bengaluru, Karnataka, IN;

Inventors:

Biman Chattopadhyay, Bengaluru, IN;

Ravi Mehta, Bengaluru, IN;

Rajesh V., Bengaluru, IN;

Assignee:

SILAB TECH PVT. LTD., Bengaluru, Karnataka, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01); H03H 7/40 (2006.01); H03K 5/159 (2006.01); H04L 25/03 (2006.01); H04B 1/16 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04B 1/16 (2013.01);
Abstract

A decision feedback equalizer (DFE) includes first through sixth flip-flops, and first and second summer circuits. The first through fourth flip-flops sample an analog input signal received at the first and second summer circuits, detect the logic level of a data bit in the analog input signal and generate the first through fourth compensated signals. The first multiplexer outputs at least one of the first and second compensated signals as a first feedback signal, based on a fourth feedback signal generated by the sixth flip-flop. The second multiplexer outputs at least one of the third and fourth compensated signals as a second feedback signal, based on a third feedback signal generated by the fifth flip-flop. The first and second feedback signals are multiplied by a weight coefficient and fed back to the first and second summer circuit, respectively, to compensate an error in the analog input signal.


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