The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Nov. 09, 2015
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

Lewis B. Aronson, Los Altos, CA (US);

Lucy G. Hosking, Santa Cruz, CA (US);

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2013.01); H04B 10/40 (2013.01); G01M 11/00 (2006.01); G01M 99/00 (2011.01); H04B 10/079 (2013.01); H04B 10/07 (2013.01);
U.S. Cl.
CPC ...
H04B 10/40 (2013.01); G01M 11/00 (2013.01); G01M 99/002 (2013.01); H04B 10/07 (2013.01); H04B 10/0799 (2013.01); H04B 2210/08 (2013.01);
Abstract

The circuit monitors operation of an optoelectronic transceiver that includes a laser transmitter and a photodiode receiver. The circuit includes analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value corresponding to a second operating condition. The circuit also includes a memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address. The circuit includes an interface configured to enable a host external to the optoelectronic transceiver to access the first digital value using the first address and to access the second digital value using the second address.


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