The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Apr. 08, 2015
Applicant:

Lockheed Martin Corporation, Bethesda, MD (US);

Inventors:

Wilbur Lew, Mount Laurel, NJ (US);

Roland Cadotte, Jr., Freehold, NJ (US);

Assignee:

LOCKHEED MARTIN CORPORATION, Bethesda, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 17/14 (2006.01); H03F 3/04 (2006.01); H03F 3/30 (2006.01);
U.S. Cl.
CPC ...
H03K 17/145 (2013.01); H03F 3/04 (2013.01); H03F 3/302 (2013.01); H03F 2200/18 (2013.01); H03F 2200/451 (2013.01); H03K 17/687 (2013.01); H03K 2217/0054 (2013.01);
Abstract

A gate pulsing gate ladder circuit includes a series connected resistor ladder with bond pads connected to the resistor ladder between adjacent resistors. An electrical node is positioned between a first and second resistor of the resistor ladder. The electrical node is electrically connected to a gate electrode of a field effect transistor (FET). A power supply produces a constant power voltage that is applied to a pre-selected bond pad to produce a desired bias voltage at the gate electrode of the FET. A selectable gate enable voltage source is connected to an and of the resistor ladder at the first resistor and is configured to produce a first and second voltage level that when combined with the constant power voltage produces a voltage level that causes the FET to be in a conducting state or non-conducting state, respectively.


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