The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jul. 12, 2014
Applicant:

Agency for Science, Technology and Research, Singapore, SG;

Inventors:

Kok Leong Chang, Singapore, SG;

Jie Zhang, Singapore, SG;

Weng Yew Lee, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/00 (2006.01); H05K 5/00 (2006.01); H01H 9/00 (2006.01); H04L 7/00 (2006.01); H03H 11/26 (2006.01); H03K 5/05 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H03K 5/05 (2013.01); H05K 1/0248 (2013.01); H05K 1/0393 (2013.01); H05K 1/095 (2013.01); H05K 1/16 (2013.01); Y10T 29/49126 (2015.01);
Abstract

In various embodiments, a printed circuit arrangement may be provided. The printed circuit arrangement may include a processor circuit. The printed circuit arrangement may further include a printed main circuit arrangement in electrical connection with a first input node of the processor circuit. The printed main circuit arrangement may be configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal. The printed circuit arrangement may further include a printed reference circuit arrangement in electrical connection with a second input node of the processor circuit. The printed reference circuit arrangement may be configured to receive a further input signal, may have a second delay and may be configured such that the second delay adapts to the first delay.


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