The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Dec. 11, 2015
Applicant:

Research & Business Foundation Sungkyunkwan University, Suwon-si, KR;

Inventors:

Kang Yoon Lee, Seoul, KR;

Sang Yun Kim, Suwon-si, KR;

Young Jun Park, Daegu-si, KR;

Dong Soo Lee, Dangjin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03B 19/14 (2006.01); H03K 3/03 (2006.01);
U.S. Cl.
CPC ...
H03B 19/14 (2013.01); H03K 3/0315 (2013.01); H03B 2200/007 (2013.01); H03B 2200/0074 (2013.01);
Abstract

An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.


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