The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Dec. 09, 2013
Applicant:

Timothy Weidman, Sunnyvale, CA (US);

Inventor:

Timothy Weidman, Sunnyvale, CA (US);

Assignee:

SunPower Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/068 (2012.01); H01L 31/0216 (2014.01); H01L 31/0224 (2006.01); H01L 31/0352 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/068 (2013.01); H01L 31/02167 (2013.01); H01L 31/022441 (2013.01); H01L 31/035272 (2013.01); H01L 31/182 (2013.01); H01L 31/1876 (2013.01); Y02E 10/546 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.


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