The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Dec. 28, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Masahiro Hikita, Hyogo, JP;

Hideyuki Okita, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/205 (2006.01); H01L 29/207 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/1066 (2013.01); H01L 29/205 (2013.01); H01L 29/207 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01);
Abstract

A semiconductor device includes a substrate, a semiconductor layer stacked body, and a source electrode and a drain electrode formed on the semiconductor layer stacked body. The semiconductor layer stacked body includes a first nitride semiconductor layer formed on the substrate, and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The semiconductor device further includes a third nitride semiconductor layer formed on the second nitride semiconductor layer and disposed between the source electrode and the drain electrode, and a gate electrode formed on the third nitride semiconductor layer. The semiconductor device includes a first magnesium-containing region having a magnesium concentration of 1×10cmor more that is provided right under the third nitride semiconductor layer, from an upper surface of the second nitride semiconductor layer to a position lower than an interface between the first nitride semiconductor layer and the second nitride semiconductor layer.


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