The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jul. 24, 2013
Applicant:

Newport Fab, Llc Dba Jazz Semiconductor, Newport Beach, CA (US);

Inventors:

Paul D. Hurwitz, Irvine, CA (US);

Edward Preisler, San Clemente, CA (US);

Hadi Jebory, Irvine, CA (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/737 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0642 (2013.01); H01L 21/486 (2013.01); H01L 21/76224 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 29/66242 (2013.01); H01L 29/7378 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.


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