The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jan. 11, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae Hwan Lee, Seoul, KR;

Tae Yong Kwon, Suwon-si, KR;

Sang Su Kim, Yongin-si, KR;

Chang Jae Yang, Seoul, KR;

Jung Han Lee, Anyang-si, KR;

Hwan Wook Choi, Yongin-si, KR;

Yeon Cheol Heo, Suwon-si, KR;

Sang Hyuk Hong, Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/7848 (2013.01); H01L 29/7849 (2013.01);
Abstract

Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.


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