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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9576931 B1

PDFFull Text
Date of Patent:
Feb. 21, 2017

Filed:

Feb. 19, 2016

Method for fabricating wafer level package

Applicant:

Inotera Memories, Inc., Taoyuan, TW;

Inventor:

Shing-Yih Shih, New Taipei, TW;

Assignee:

INOTERA MEMORIES, INC., Taoyuan, TW;

Attorneys:

Winston Hsu

Scott Margo

Primary Examiner:

Mohammad Choudhry

Int. Cl.
CPC ...
B65D 85/00 (2006.01); H01L 33/48 (2010.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/3105 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/31053 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 24/11 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/13024 (2013.01);
Abstract

A method for fabricating a wafer level package is disclosed. A carrier is provided. A redistributed layer (RDL) layer is formed on the carrier. Semiconductor dies are mounted on the RDL layer. The semiconductor dies are molded with a molding compound, thereby forming a molded wafer. A grinding process is then performed to remove a central portion of the molding compound, thereby forming a recess and an outer peripheral ring portion surrounding the recess. The carrier is then removed to expose a lower surface of the RDL layer. Solder bumps or solder balls are formed on the lower surface of the RDL layer.

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Shih, Shing-Yih. (2017). Method for fabricating wafer level package (U.S. Patent No. 9576931). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9576931

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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