The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

May. 26, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Dong-Hyun Lee, Yongin, KR;

Ki-Yong Lee, Yongin, KR;

Jin-Wook Seo, Yongin, KR;

Tae-Hoon Yang, Yongin, KR;

Yun-Mo Chung, Yongin, KR;

Byoung-Keon Park, Yongin, KR;

Kil-Won Lee, Yongin, KR;

Jong-Ryuk Park, Yongin, KR;

Bo-Kyung Choi, Yongin, KR;

Byung-Soo So, Yongin, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/477 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02672 (2013.01); H01L 21/0206 (2013.01); H01L 21/02488 (2013.01); H01L 21/02491 (2013.01); H01L 21/02532 (2013.01); H01L 21/477 (2013.01); H01L 27/1277 (2013.01); H01L 27/3244 (2013.01); H01L 29/66757 (2013.01); H01L 29/78603 (2013.01); H01L 29/78675 (2013.01);
Abstract

A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.


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