The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Sep. 25, 2013
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Hirotoshi Akaike, Tokyo, JP;

Katsuya Tanaka, Tokyo, JP;

Makio Mizuno, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/36 (2006.01); G06F 13/42 (2006.01); G06F 3/06 (2006.01); G06F 13/14 (2006.01); G06F 13/362 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 3/06 (2013.01); G06F 13/14 (2013.01); G06F 13/362 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01);
Abstract

In a storage device applying PCIe to a back-end network connection, in order to be capable of allocating bus numbers and making a PCIe switch expanded afterwards usable, it is necessary to once reset all PCIe switches. To dissolve this necessity, PCIe switches of the back-end network of the storage device are connected in series, a range of continuous bus numbers that are managed and stored in bus number management table is allocated for the back-end network connection, and when expanding the PCIe switch, the bus numbers are allocated in ascending order from a minimum value of the allocatable bus numbers to each of a link between the PCIe switches and to a virtual PCI bus within the PCIe switch, and the bus numbers are allocated in descending order from a maximum value of the allocatable bus numbers to the link between the PCIe switch and a drive.


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