The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Nov. 20, 2013
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Yong Deok Cho, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 8/08 (2006.01); G11C 8/12 (2006.01); G11C 8/18 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G06F 12/02 (2013.01); G11C 8/08 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 7/18 (2013.01); G11C 2207/005 (2013.01);
Abstract

A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.


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