The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Apr. 06, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Vincenzo Condorelli, Poughkeepsie, NY (US);

Silvio Dragone, Winterthur, CH;

William Santiago-Fernandez, Poughkeepsie, NY (US);

Tamas Visegrady, Zurich, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 9/44 (2006.01); G06F 21/57 (2013.01); G06F 12/02 (2006.01); G06F 13/40 (2006.01); G06F 9/445 (2006.01); G05B 19/05 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4403 (2013.01); G06F 8/665 (2013.01); G06F 9/44505 (2013.01); G06F 21/575 (2013.01); G05B 19/056 (2013.01); G06F 8/63 (2013.01); G06F 8/65 (2013.01); G06F 9/4401 (2013.01); G06F 11/1433 (2013.01); G06F 12/0246 (2013.01); G06F 13/4022 (2013.01);
Abstract

A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.


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