The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Nov. 16, 2015
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Liang Zuo, San Jose, CA (US);

Zhihao Xu, Sunnyvale, CA (US);

Bi Yuan, San Jose, CA (US);

Liping Deng, Cupertino, CA (US);

Yuxin Wang, Sunnyvale, CA (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H04N 3/14 (2006.01); H04N 5/378 (2011.01); H04N 5/369 (2011.01); H04N 5/376 (2011.01); H04N 5/225 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H04N 5/2253 (2013.01); H04N 5/3698 (2013.01); H04N 5/3765 (2013.01);
Abstract

A ramp generator for use in readout circuitry includes an integrator coupled to receive a ramp generator input reference signal to generate a reference ramp signal coupled to be received by an analog to digital converter. A power supply compensation circuit that is coupled to generate the ramp generator input reference signal includes a delay circuit including a variable resistor and a filter capacitor coupled to receive a power supply signal. The variable resistor is tuned to match a delay ripple from the power supply to a bitline output. A capacitive voltage divider is coupled to the delay circuit to generate the ramp generator input reference signal. The capacitive voltage divider includes a first variable capacitor coupled to a second variable capacitor that are tuned to provide a capacitance ratio that matches a coupling ratio from the power supply to the bitline output.


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