Decision feedback equalizer and receiver circuit

Abstract

A plurality of comparator circuits output results of comparing a pulse amplitude modulated input signal having four or more values with a plurality of first thresholds. A selection section decides a value of the input signal at certain timing by selecting one of the comparison results on the basis of a result of deciding a value of the input signal at previous timing. A threshold setting section generates the first thresholds from a plurality of third thresholds obtained by adding an offset value based on magnitude of inter-symbol interference corresponding to each value to one of second thresholds whose number is based on the number of values, on the basis of an average value of third thresholds greater than a second threshold or third thresholds smaller than the second threshold and an adjustment value based on the decision result and sets the first thresholds in the comparator circuits.