The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Oct. 02, 2014
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Xiaobing Lee, Santa Clara, CA (US);

Chunlei Dong, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/23 (2006.01); G06F 13/28 (2006.01); H03M 13/37 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
H03M 13/235 (2013.01); G06F 12/0875 (2013.01); G06F 13/28 (2013.01); H03M 13/373 (2013.01); G06F 12/0868 (2013.01); G06F 2212/403 (2013.01); G06F 2212/603 (2013.01);
Abstract

System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two.


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