The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9571113 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2017

Filed:

Feb. 15, 2013
Applicant:

National University Corporation Hokkaido University, Sapporo-shi, Hokkaido, JP;

Inventor:

Masayuki Ikebe, Sapporo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); G04F 10/00 (2006.01); H03M 1/56 (2006.01); H04N 5/378 (2011.01); H03M 1/14 (2006.01); H04N 5/374 (2011.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); G04F 10/005 (2013.01); H03M 1/14 (2013.01); H03M 1/56 (2013.01); H04N 5/378 (2013.01); H04N 5/374 (2013.01);
Abstract

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.


Find Patent Forward Citations

Ikebe, Masayuki. (2017). Integral a/d converter and cmos image sensor (U.S. Patent No. 9571113). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9571113

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