The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
May. 12, 2015
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Young-Suk Seo, Gyeonggi-do, KR;
Da-In Im, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/081 (2006.01); G11C 7/22 (2006.01); H03L 7/16 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); G11C 7/22 (2013.01); H03L 7/0814 (2013.01); H03L 7/16 (2013.01); G11C 7/222 (2013.01);
Abstract
A delay locked loop (DLL) circuit may include: a DLL unit suitable for generating an internal clock by delaying an external clock by a delay amount required for locking; a single-to-differential divider suitable for generating multi-phase divided clocks at a specific edge of the internal clock; and a phase correction unit suitable for correcting a phase error between the multi-phase divided clocks.
Seo, Young-Suk. (2017). Delay locked loop circuit (U.S. Patent No. 9571106). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9571106
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile