The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Mar. 20, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Yun-Hyuck Ji, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7842 (2013.01); H01L 21/28052 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 27/092 (2013.01); H01L 29/4925 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/785 (2013.01); H01L 29/7845 (2013.01);
Abstract
A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.