The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Nov. 25, 2014
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventors:

Rahul Sharangpani, Fremont, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Senaka Krishna Kanakamedala, Milpitas, CA (US);

Sateesh Koka, Milpitas, CA (US);

Yao-Sheng Lee, Tampa, FL (US);

George Matamis, Danville, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 29/495 (2013.01); H01L 29/7883 (2013.01);
Abstract

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.


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