The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Apr. 23, 2015
Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
Shanghai Lexvu Opto Microelectronics Technology Co., Ltd., Shanghai, CN;
Jianhong Mao, Shanghai, CN;
Fengqin Han, Shanghai, CN;
Zhiwei Wang, Shanghai, CN;
Wenfen Chang, Shanghai, CN;
SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD., Shanghai, CN;
Abstract
The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.