The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

May. 04, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Priyankar Mathuria, Bangalore, IN;

Gururaj Shamanna, Bangalore, IN;

VRC Krishna Teja Kunisetty, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/419 (2006.01); H03K 3/356 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/106 (2013.01); G11C 7/1051 (2013.01); H03K 3/037 (2013.01); H03K 3/356104 (2013.01);
Abstract

An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node.


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