The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Oct. 11, 2013
Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;
Akihisa Iwamoto, Osaka, JP;
Masami Ozaki, Osaka, JP;
Tomohiko Nishimura, Osaka, JP;
Kohji Saitoh, Osaka, JP;
Masaki Uehata, Osaka, JP;
Jun Nakata, Osaka, JP;
Sharp Kabushiki Kaisha, Sakai, JP;
Abstract
A gate driver () which is provided by an IGZO-GDM and a level shifter circuit () are connected to each other via a first through a fifth wires (OLthrough OL). Each wire (OL) is connected to a discharge unit (). If an electric power supply to a first through a fifth output circuits (OCthrough OC) in the level shifter circuit () becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OCthrough OC) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit () into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.