The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Apr. 20, 2012
Applicants:

Alper Buyuktosunoglu, White Plains, NY (US);

Philip G. Emma, Danbury, CT (US);

Allan M. Hartstein, Chappaqua, NY (US);

Michael B. Healy, White Plains, NY (US);

Krishnan Kunjunny Kailas, Tarrytown, NY (US);

Inventors:

Alper Buyuktosunoglu, White Plains, NY (US);

Philip G. Emma, Danbury, CT (US);

Allan M. Hartstein, Chappaqua, NY (US);

Michael B. Healy, White Plains, NY (US);

Krishnan Kunjunny Kailas, Tarrytown, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 15/78 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7867 (2013.01); H01L 25/0657 (2013.01); H01L 2924/0002 (2013.01); Y02B 60/1207 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.


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