The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Dec. 19, 2008
Applicant:

Serag M. Gadelrab, Kanata, CA;

Inventor:

Serag M. GadelRab, Kanata, CA;

Assignee:

ATI Technologies ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 1/32 (2006.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/02 (2013.01); G06F 1/32 (2013.01); G06F 12/08 (2013.01); G06F 12/10 (2013.01); G06F 12/1027 (2013.01); G06F 12/0815 (2013.01); G06F 12/122 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/681 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of 'hardware memory mover' does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth.


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