The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

May. 02, 2016
Applicant:

Xitore, Inc., Mission Viejo, CA (US);

Inventors:

Mike Hossein Amidi, Lake Forest, CA (US);

Hossein Hashemi, Laguna Niguel, CA (US);

Assignee:

Xitore, Inc., Mission Viejo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G11C 29/52 (2006.01); G11C 8/06 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30 (2013.01); G06F 3/0605 (2013.01); G06F 3/0619 (2013.01); G06F 3/0635 (2013.01); G06F 3/0655 (2013.01); G06F 3/0659 (2013.01); G06F 3/0661 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 11/10 (2013.01); G06F 11/1004 (2013.01); G06F 11/1068 (2013.01); G06F 12/0223 (2013.01); G06F 12/06 (2013.01); G06F 12/0638 (2013.01); G06F 12/0802 (2013.01); G06F 12/0888 (2013.01); G06F 12/10 (2013.01); G11C 29/52 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/152 (2013.01); G06F 2212/261 (2013.01); G06F 2212/401 (2013.01); G06F 2212/403 (2013.01); G11C 8/06 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A method of storing data is provided. The method includes receiving commands from a system memory controller of a computer system. The commands include logical addresses and are received by a computer memory device comprising a parallel memory interface operatively coupled to the system memory controller and operatively coupled to a non-volatile memory. The method further includes responding to the commands by translating the received logical addresses to corresponding physical addresses of the non-volatile memory, receiving data from the system memory controller by the parallel memory interface, and storing the data at memory locations of the non-volatile memory corresponding to the physical addresses.


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