The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9568940 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2017

Filed:

Dec. 05, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gerald K. Bartley, Rochester, MN (US);

Darryl J. Becker, Rochester, MN (US);

William P. Hovis, Rochester, MN (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 1/04 (2006.01); H01L 25/065 (2006.01); H01L 21/66 (2006.01); G06F 13/40 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/04 (2013.01); H01L 22/20 (2013.01); H01L 25/0657 (2013.01); G06F 13/4086 (2013.01); H01L 22/14 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/37001 (2013.01);
Abstract

An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus.


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