The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Dec. 09, 2014
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Naoki Il, Suwa, JP;

Katsuhiko Maki, Chino, JP;

Takashi Kurashina, Matsumoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01C 19/00 (2013.01); G01C 19/5776 (2012.01); G01D 5/12 (2006.01); G01C 19/5614 (2012.01); H03B 5/36 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
G01C 19/5776 (2013.01); G01C 19/5614 (2013.01); G01D 5/12 (2013.01); H03B 5/364 (2013.01); H03L 7/0814 (2013.01); H03L 7/0816 (2013.01);
Abstract

A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.


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