The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

May. 22, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Qi Ye, San Diego, CA (US);

Steven James Dillen, San Diego, CA (US);

Animesh Datta, San Diego, CA (US);

Zhengyu Duan, San Diego, CA (US);

Satyanarayana Sahu, San Diego, CA (US);

Praveen Narendranath, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 5/131 (2014.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 5/131 (2013.01);
Abstract

A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionallyat a delay module output, where Iis a function of I and Iis a function of Iand B, and where I is a delay module input, Bis a first input bit, and Iis a first net input.


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