The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Apr. 17, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Michael P. Chudzik, Danbury, CT (US);

Martin M. Frank, Bronx, NY (US);

Herbert L. Ho, New Windsor, NY (US);

Mark J. Hurley, Poughkeepsie, NY (US);

Rashmi Jha, Beacon, NY (US);

Naim Moumen, Walden, NY (US);

Vijay Narayanan, New York, NY (US);

Dae-Gyu Park, Poughquag, NY (US);

Vamsi K. Paruchuri, New York, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/49 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/823842 (2013.01); H01L 27/092 (2013.01); H01L 29/4958 (2013.01); H01L 29/517 (2013.01);
Abstract

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.


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