The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Jun. 19, 2013
Applicant:

Joled Inc., Tokyo, JP;

Inventors:

Atsushi Sasaki, Hyogo, JP;

Eiichi Satoh, Hyogo, JP;

Hirofumi Higashi, Hyogo, JP;

Assignee:

JOLED INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 27/32 (2006.01); H01L 21/311 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 51/52 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3244 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 29/78693 (2013.01); H01L 51/5212 (2013.01); H01L 2227/323 (2013.01);
Abstract

A method of manufacturing a thin film transistor (TFT) substrate in which a TFT including an oxide semiconductor layer is formed, the method including: forming an insulating layer to cover the oxide semiconductor layer; and forming an opening in the insulating layer, wherein the insulating layer includes a first film, a second film which is provided above the first film and is an aluminum oxide film, and a third film which is provided above the second film and is a film including silicon, and the forming of an opening includes: forming a resist pattern above the third film; processing the third film by dry etching; and processing the second film by wet etching.


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